By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)
The awareness of sign sampling and quantization at excessive pattern premiums with low strength dissipation is a vital aim in lots of functions, includ ing transportable video units reminiscent of camcorders, own conversation units reminiscent of instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic info detection, and so forth. This paper describes structure and circuit methods for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive velocity is taken to suggest sampling premiums above 1 Mhz. within the first part the dif ferent conversion suggestions acceptable during this variety of pattern premiums is dis stubborn. Following that the actual difficulties linked to strength minimization in video-rate pipeline ADCs is mentioned. those contain optimi zation of capacitor sizes, layout of low-voltage transmission gates, and opti mization of switched capacitor achieve blocks and operational amplifiers for minimal energy dissipation. for example of the appliance of those tech niques, the layout of a power-optimized lO-bit pipeline reduction converter (ADC) that achieves =1. sixty seven mW consistent with MS/s of sampling fee from 1 MS/s to twenty MS/s is defined. 2. suggestions for CMOS Video-Rate reduction Conversion Analog-to-digital conversion options should be labeled in lots of methods. One handy technique of evaluating suggestions is to envision the variety of "analog clock cycles" required to supply one potent output pattern of the sign being quantized.
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Extra resources for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
21. The inaccurate biasing due to the large resistors, however, remains. If the resistors are eliminated from the circuit as shown Fig. 21, the circuit of Fig. 22 is obtained. The sum of the base-emitter voltages is kept constant by the two translinear loops . The transistors Q] and Q2 form a loop with a very high resistance, which prevents a loss of signal current. The coupling of the class-AB circuit is so strong that one of the signal current-sources, lin] and lin2' will suffice to drive the output transistors.
The 3-times current mirrors control the gm' when the complementary input stage gradually switches from one input pair to the other. This change of the offset voltage degrades the CMMR in the transition regions. a-;'~" 1 o;-------~~--------------~~----~ Fig. 17. gm versus the transconductance for the complementary input stage with three-times current mirror. Iv. Voltage and Current Emcient Output Stages Output stages for low-voltage low-power applications should have a railto-rail output range and should be class-AB biased.
I ~----~~~--~-----L----~----~--~~~VEE Fig. 28. Three-stage amplifier with nested Miller compensation. t Voltage gain (dB) frequency (Hz) - Fig. 29. The open-loop gain o/the three-stage amplifier with nested Miller compensation. fier with two dominant poles, /} and h. The capacitor CM } closes the first Miller loop which splits h and h to h' and h', respectively. The pole h' is 3 dB below the unity-gain frequency, as is shown in Fig. 29. Therefore, the intermediate and output stage can now be conceived as one stage with one dominant pole h'.