By Steve Leibson
Microprocessor cores used for SOC layout are the direct descendents of Intel’s unique 4004 microprocessor. simply as packaged microprocessor ICs range generally of their attributes, so do microprocessors packaged as IP cores. even if, SOC designers nonetheless evaluate and choose processor cores the best way they formerly in comparison and chosen packaged microprocessor ICs. the massive challenge with this option strategy is that it assumes that the legislation of the microprocessor universe have remained unchanged for many years. This assumption isn't any longer valid.
Processor cores for SOC designs could be way more plastic than microprocessor ICs for board-level process designs. Shaping those cores for particular functions produces far better processor potency and lots more and plenty reduce process clock premiums. jointly, Tensilica’s Xtensa and Diamond processor cores represent a relations of software-compatible microprocessors masking an incredibly vast functionality variety from uncomplicated keep an eye on processors, to DSPs, to 3-way superscalar processors. but all of those processors use a similar software-development instruments in order that programmers acquainted with one processor within the family members can simply change to another.
This e-book emphasizes a processor-centric MPSOC (multiple-processor SOC) layout variety formed by way of the realities of the 21st-century and nanometer silicon. It advocates the task of projects to firmware-controlled processors at any time when attainable to maximise SOC flexibility, reduce strength dissipation, lessen the scale and variety of hand-built common sense blocks, scale down the linked verification attempt, and reduce the general layout threat.
· a vital, no-nonsense consultant to the layout of 21st-century mega-gate SOCs utilizing nanometer silicon.
· Discusses contemporary key concerns affecting SOC layout, according to author's a long time of non-public event in constructing huge electronic platforms as a layout engineer whereas operating at Hewlett-Packard's laptop desktop department and at EDA computing device pioneer Cadnetix, and protecting such subject matters as an award-winning expertise journalist and editor-in-chief for EDN journal and the Microprocessor Report.
· Explores conventionally approved obstacles and perceived limits of processor-based procedure layout after which explodes those man made constraints via a clean outlook on and dialogue of the detailed skills of processor cores designed particularly for SOC design.
· Thorough exploration of the evolution of processors and processor cores used for ASIC and SOC layout with a glance at the place the has come from, and the place it is going.
· Easy-to-understand causes of the features of configurable and extensible processor cores via an in depth exam of Tensilica's configurable, extensible Xtensa processor center and 6 pre-configured Diamond cores.
· the main complete overview on hand of the sensible points of configuring and utilizing a number of processor cores to accomplish very tough and bold SOC rate, functionality, and tool layout pursuits.