Computer Engineering and Technology: 17th CCF Conference, by Jianfeng Zhang, Wei Ding, Hengzhu Liu (auth.), Weixia Xu,

By Jianfeng Zhang, Wei Ding, Hengzhu Liu (auth.), Weixia Xu, Liquan Xiao, Chengyi Zhang, Jinwen Li, Liyan Yu (eds.)

This publication constitutes the refereed complaints of the seventeenth nationwide convention on machine Engineering and expertise, NCCET 2013, held in Xining, China, in July 2013. The 26 papers awarded have been rigorously reviewed and chosen from 234 submissions. they're geared up in topical sections named: program particular Processors; verbal exchange structure; computing device program and software program Optimization; IC layout and attempt; Processor structure; expertise at the Horizon.

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Extra resources for Computer Engineering and Technology: 17th CCF Conference, NCCET 2013, Xining, China, July 20-22, 2013. Revised Selected Papers

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Compared with FPGA, ASIC usually could provide a system with better performance with respect to speed and space requirements. However, the reconfiguration of ASIC-based designs will cost more time and expenses than FPGA-based ones. As for the market data feeds, the format and protocol are changing in a relatively more frequent trend. The long time cycle and expensive cost of the reconfiguration of an ASIC-based design lead to the inappropriateness to design a market data feeds accelerator based on ASIC.

The reason is that there is one RNS-to-binary unit in this solution, increasing the area burden. 3. [10] improves the Cox-Rower architecture, which makes it suitable for ECC over GF(p) and leads to faster speed of scalar multiplication. But it cannot support RSA. In conclusion, the proposed crypto-processor performs a kind of better tradeoff among performance, area and flexibility. A Unified Cryptographic Processor for RSA and ECC in RNS 31 Fig. 8. 8 shows the chip layout of the proposed crypto-processor and its features.

Com Abstract. Market data feeds present the current state of the financial market to the customers, with the demand of fast transmission and instant response. The OPRA format with the FAST protocol is one of the most widely-used formats of the market data feeds. This paper provides an accelerator based on FPGA for processing the market data feeds in OPRA format. The accelerator focuses on encoding and decoding the data feeds concerning five of the most important categories, namely categories a, d, k, q and N.

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