Design Automation for Timing-Driven Layout Synthesis by Sachin S. Sapatnekar, Sung-Mo Kang (auth.)

By Sachin S. Sapatnekar, Sung-Mo Kang (auth.)

Moore's legislation [Noy77], which anticipated that the variety of units in­ tegrated on a chip will be doubled each years, was once exact for a few years. just recently has the extent of integration be­ gun to decelerate a little as a result actual limits of integration know-how. Advances in silicon know-how have allowed Ie layout­ ers to combine quite a lot of million transistors on a chip; even a complete process of average complexity can now be carried out on a unmarried chip. to maintain speed with the expanding complexity in very huge scale built-in (VLSI) circuits, the productiveness of chip designers must bring up on the similar cost because the point of integration. with out such a rise in productiveness, the layout of complicated platforms will not be feasible inside an inexpensive time frame. The quickly expanding complexity of VLSI circuits has made de- 1 2 creation signal automation an absolute necessity, because the required bring up in productiveness can in basic terms be complete with using subtle layout instruments. Such instruments additionally allow designers to accomplish trade-off analyses of other common sense implementations and to make well-informed layout decisions.

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2. 10: The Penfield-Rubenstein bounds. 10. At) = viet). 20) is conservative, the expression on the right-hand side is a good qualitative indicator of the distance between the bounds. It may be pointed out that the functions lli and Vi are one-to-one functions of t. Hence, bounds on the delay t(V), the time required by the step response to cross a voltage threshold V, can easily be obtained from the above expression. lli. - TRI,. 22) A more detailed discussion on the tightness of these bounds can be found in [Wya87].

40 DELAY ESTIMATION This experiment is then repeated with input ramps of different slew rates, producing a delay table with four delay values (namely, and ~t2' ~tl for type 0 and type 1) for each value of ~in. The procedure is repeated to generate delay tables for the standard primitives 2 and 3. The tables in all three cases are one-dimensional, since ~in is the only variable. For primitives 4 and 5, CI, RD and Rp have to be specified to describe the circuit completely. This is done with the help of parameters (3 and,.

Lli. - TRI,. 22) A more detailed discussion on the tightness of these bounds can be found in [Wya87]. 3. 3 31 Macromodeling Macromodeling [Mat85, Che88] is a technique that was developed to help analyze large circuits. The underlying philosophy is that the information that is of interest to circuit designers is at the gate level, rather than at the transistor level. Hence, individual logic blocks, such as gates, are replaced by equivalent macromodels. This serves the purpose of eliminating all nodes internal to a logic gate, thereby reducing the number of nodes and, therefore, the computational complexity.

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