Designers' Guide to EN 1994-2: Eurocode 4: Design of by C.R. Hendy and R.P. Johnson (Editors)

By C.R. Hendy and R.P. Johnson (Editors)

This ebook is an authoritative consultant to the technical heritage and functional facets of this ecu code of perform that might supersede corresponding nationwide codes within the international locations which are contributors of the eu Standardisation business enterprise - CEN (Comit?© Europ?©en de Normalisation).

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With the increase in clock frequency and the decrease in gate length, together with the increase in number of transistors in a chip, the tremendous increase in power consumption becomes the main issue. In order to suppress the power consumption, supply voltage should be reduced aggressively, as shown in Fig. 16c. In order to maintain high performance under the low supply voltage, gate insulator thickness should be reduced very tremendously. 8 nm in Intel’s roadmap, as shown in Fig. 16d. In terms of total gate leakage current of an entire LSI chip for use for mobile cellular phone, 2 nm is already too thin, in which standby power consumption should be minimized.

Fiegna, M. Ono, M. Saito, and H. Iwai, ‘‘Tenth micron P-MOSFET’s with ultra-thin epitaxial channel layer grown by ultra-high vacuum CVD,’’ IEDM Tech. , pp. 433–436, December, 1993. 8. T. Ohguro, N. Sugiyama, K. Imai, K. Usuda, M. Saito, T. Yoshitomi, M. S. Momose, and H. 1 mm epitaxial Si channel n-MOSFETs grown by UHV-CVD,’’ Symp. , pp. 21–22, 1995. 2007 5:06pm Compositor Name: VBalamugundan Trends and Projections for the Future of Scaling and Future Integration Trends 1-29 9. T. Yoshitomi, M.

Dukovic, R. Wachnik, H. Rathore, R. Schulz, L. Su, S. Luce, and J. 25 mm CMOS ULSI technology,’’ IEDM Tech. , pp. 773–776, 1997. 53. N. H. S. T. Y. J. S. H. Y. S. 15 mm DRAM generation and beyond,’’ Symp. , pp. 33–34, 1999. 54. T. Eshita, K. Nakamura, M. Mushiga, A. Itoh, S. Miyagaki, H. Yamawaki, M. Aoki, S. Kishii, and Y. 5-mm 64-kbit embedded SBT FeRAM using a new low temperature SBT deposition technique,’’ Symp. , pp. 139–140, 1999. 55. H. Takato, H. Koike, T. Yoshida, and H. Ishiuchi, ‘‘Process integration trends for embedded DRAM,’’ Proc.

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