Digital Design and Fabrication by Vojin G. Oklobdzija

By Vojin G. Oklobdzija

In line with great development and new applied sciences within the semiconductor undefined, this quantity is prepared into 5, information-rich sections. electronic layout and Fabrication surveys the most recent advances in machine structure and layout in addition to the applied sciences used to fabricate and try them. that includes contributions from prime specialists, the booklet additionally incorporates a new part on reminiscence and garage as well as a brand new bankruptcy on nonvolatile reminiscence applied sciences. constructing complex recommendations, this sharply concentrated e-book: * Describes new applied sciences that experience turn into riding elements for the digital undefined * comprises new details on semiconductor reminiscence circuits, whose improvement most sensible illustrates the exceptional development encountered by means of the fabrication and know-how zone * includes a part devoted to matters with regards to approach energy intake * Describes reliability and testability of desktops * Pinpoints traits and state of the art advances in fabrication and CMOS applied sciences * Describes functionality overview measures, that are the base line from the user’s viewpoint * Discusses layout concepts used to create sleek desktops, together with high-speed laptop mathematics and high-frequency layout, timing and clocking, and PLL and DLL layout

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With the increase in clock frequency and the decrease in gate length, together with the increase in number of transistors in a chip, the tremendous increase in power consumption becomes the main issue. In order to suppress the power consumption, supply voltage should be reduced aggressively, as shown in Fig. 16c. In order to maintain high performance under the low supply voltage, gate insulator thickness should be reduced very tremendously. 8 nm in Intel’s roadmap, as shown in Fig. 16d. In terms of total gate leakage current of an entire LSI chip for use for mobile cellular phone, 2 nm is already too thin, in which standby power consumption should be minimized.

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