By Lars Wehmeyer
Pace advancements in reminiscence structures haven't saved velocity with the rate advancements of processors, resulting in embedded structures whose functionality is restricted by way of the reminiscence. This e-book offers layout ideas for speedy, energy-efficient and timing-predictable reminiscence structures that in attaining excessive functionality and occasional power intake. furthermore, using scratchpad stories considerably improves the timing predictability of the whole approach, resulting in tighter worst case execution time bounds.
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Additional info for Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation
The main drawback of Tiwari’s model is the fact that only the processor itself is being modeled, thus neglecting the memory subsystem. This can lead to a mismatch between the predicted energy consumption of the processor and the energy dissipation of the complete system, including the memory. Therefore, Tiwari’s model was extended by Steinke et al. [SKWM01] to also account for the energy consumed within the memories. Since their energy model is also used for the ARM7 in this work, it will be described in detail in the following section.
On bus lines that are known to have a high capacitance and therefore consume a relevant amount of energy when their value changes. The measured switching activity can then be used as a measure for the dissipated energy. However, the quantitative impact of bus toggling on overall energy consumption can vary signiﬁcantly. Generally, such simulation results require validation against real hardware to show their applicability and the margin of error. Assuming that the simulation is performed using a VHDL model of the processor to be measured, then commonly available VHDL simulators can be used to generate information concerning the switching activity at the diﬀerent levels sketched above.
This signiﬁcantly simpliﬁes the memory timing model, since no state-dependent information has to be considered. Data sheets usually provide the memory access times in nanoseconds. By transformation to a multiple of the processor’s clock period, each type of access using SRAM memory takes a certain number of clock cycles. The scratchpad memory embedded directly on the processor die usually takes only one clock cycle per access, meaning that the processor does not have to insert any wait cycles to wait for data or instructions.