Low Power Asynchronous. Digital Signal Processing by Lewis M.J.G.

By Lewis M.J.G.

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Extra resources for Low Power Asynchronous. Digital Signal Processing

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International Symposium on Advanced Research in Asynchronous Circuits and Systems, April 1999, pp. 1 Design for low power Sources of power consumption In order to design circuits that consume as little power as possible, it is vital to understand the sources of power dissipation. In a CMOS circuit, power dissipation can be summarised by: [37] P avg = P switching + P short + P leakage (1) 2 = f C L V dd + I SC V dd + I leakage V dd (2) The first two components are the dynamic power dissipation caused by switching activity at the various nodes within the circuits, while the third component is caused by static leakage.

Full and half rate speech channels use single level cyclic redundancy coding (CRC) to check for transmission errors, with the transmitted block being discarded if an error is detected. Enhanced full-rate speech channels use a two-level cyclic redundancy code. Control channels are protected with Fire coding, a special class of cyclic code designed to correct burst errors [26]. One of a number of different convolutional coding schemes are then applied, depending on the type of data to be transmitted.

Decoding of cyclic codes can be done using very similar shift-register based circuits such as the Meggitt error trapping decoder [26]. Decoding of convolutional codes is a very much more complex matter. The most common method for decoding convolutional codes is to use the Viterbi algorithm [27]. 8). Each input bit causes a state change, and a particular symbol to be transmitted. 8 1/2 rate convolutional encoder for full-rate channels The task for the decoder is to examine the received code symbols and determine which sequence of state changes (and therefore which sequence of transmitted symbols) occurred at the encoder.

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