By Benny Akesson, Kees Goossens
Verification of real-time necessities in systems-on-chip turns into extra complicated as extra functions are built-in. Predictable and composable platforms can deal with the expanding complexity utilizing formal verification and simulation. This e-book explains the suggestions of predictability and composability and indicates find out how to practice them to the layout and research of a reminiscence controller, that is a key part in any real-time system.
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Extra resources for Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems
1 stated that the memory controller must provide useful bounds on the offered bandwidth and latency of memory transactions. This section explains how the proposed memory controller delivers on this requirement. First, we present an overview of our approach to predictability, which is based on combining predictable memories with predictable arbitration. Then, we explain how to make an SDRAM memory behave in a predictable manner, before concluding with a discussion on predictable arbitration. 1 Overview of Approach Our approach to predictable memory controllers is based on combining memories and arbiters with predictable behaviors.
The currently open row hence has to be closed and the requested row opened before the access can proceed. This results in added latency and many unused cycles on the data bus of the memory, as explained in Sect. 6. It is not possible under this assumption to guarantee that the offered bandwidth will be greater than some 10–40% of the maximum bandwidth, depending on the speed of the memory . Although this is a known bound on relevant behavior that covers all state transitions and initial states, it is not considered useful for many SoC designs, since SDRAM bandwidth is a scarce resource that must be efficiently utilized.
This prevents formal analysis techniques from being applied to many platforms, since SDRAMs are essential to satisfy large storage requirements at a reasonable cost. The reason SDRAM memories are difficult to combine with formal analysis is due to a combination of complex temporal behavior that is inherent to their architecture and contradictory requestor requirements. The next section elaborates on these problems. 6 SDRAM and Real-Time Requirements SDRAM memories are challenging to use in systems with real-time requirements because of their internal architecture.