Microprocessor Design by Rowland Cable

By Rowland Cable

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An FPU is complicated to design, although the IEEE 754 standard helps to answer some of the specific questions about implementation. It isn't always necessary to follow the IEEE standard when designing an FPU, but it certainly does help. Floating point numbers This section is just going to serve as a brief refresher on floating point numbers. For more information, see the Floating Point book. Floating point numbers are specified in two parts: the exponent (e), and the mantissa (m). 0. Floating Point Multiplication Multiplying two floating point numbers is done as such: Likewise, division can be performed by: To perform floating point multiplication then, we can follow these steps: 1.

Offset and Non-Offset Branching Many systems have capabilities to use both offset and non-offset branching. Some systems may differentiate between the two as "far jump" and "near jump", respectively, although this terminology is archaic. Instruction Decoder The Instruction Decoder reads the next instruction in from memory, and sends the component pieces of that instruction to the necessary destinations. RISC Instruction Decoder The RISC instruction decoder is typically a very simple device. Because RISC instruction words are a fixed length, the positions of the fields are fixed.

However, register files are small to implement, so we have enough space for 32 registers. The solution to this dilemma is to utilize a register bank which consists of a series of register files combined together. A register bank contains a number of register files or pages. Only one page can be active at a time, and there are additional instructions added to the ISA to switch between the available register pages. Data values can only be written to and read from the currently active register page, but instructions can exist to move data from one page to another.

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