Sequential Logic: Analysis and Synthesis by Joseph Cavanagh

By Joseph Cavanagh

Before, there has been no unmarried source for genuine electronic approach layout. utilizing either uncomplicated and complex recommendations, Sequential common sense: research and Synthesis deals an intensive exposition of the research and synthesis of either synchronous and asynchronous sequential machines.

With 25 years of expertise in designing computing gear, the writer stresses the sensible layout of kingdom machines. He essentially delineates each one step of the dependent and rigorous layout ideas that may be utilized to useful purposes. The ebook starts via reviewing the research of combinatorial good judgment and Boolean algebra, and is going directly to outline sequential machines and speak about conventional and substitute equipment for synthesizing synchronous sequential machines. the ultimate chapters take care of asynchronous sequential machines and pulse-mode asynchronous sequential machines. simply because this quantity is technology-independent, those ideas can be utilized in quite a few fields, equivalent to electric and desktop engineering in addition to nanotechnology.

By featuring every one technique intimately, expounding on a number of corresponding examples, and supplying over 500 worthy figures, Sequential common sense is a wonderful instructional on research and synthesis methods

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Extra resources for Sequential Logic: Analysis and Synthesis

Example text

When combining 0s to obtain sum terms, treat a variable value of 1 as false and a variable value of 0 as true. Thus, minterm locations 7 and 15 have variables x2 x3 x4 = 111, providing a sum term of (x2 ' + x3 ' + x4 ' ). 19 both specify the conditions where z1 is equal to 1. 18. 18 yields z1 = 1 + ˜ ˜ ˜ + 0 which generates a value of 1 for z1. 19 will cause every term to be equal to 1, such that, z1 = (1) (1) (1) = 1. 1 (d) illustrates a 5-variable Karnaugh map. To determine adjacency, the left map is superimposed on the right map.

Thus, z1 is asserted high for (x1 x2 x3 ' )'' = x1 x2 x3 '. The fourth input variable is +x4 , which specifies that x4 is active at a high voltage level. In order for the low input requirement to be met for gate 3, input x4 must be inactive. Thus, if x4 ' is true, then z1 is asserted. The complete equation for z1, therefore, is z1 = x1 ' x2 ' + x1 x2 x3 ' + x4 '. 20 (b) represents the same circuit, but in a more compact format. 21, the equation for output z1 will be obtained. The circuit is implemented using NAND gates only.

The output level is shown for each gate with the corresponding expression that generates the indicated voltage level. For example, the output of gate 3 will be at a high voltage level if the expression (x1 + x2 ) x3 ' is true. Similarly, the output of gate 5 will be at a high voltage level if the expression x1 ' x2 ' + x4 is true. 29. 16 using only NAND gates. Output z1 = {[(x1 + x2 )x3 '] [(x1 ' x2 ' ) + x4 ]} + x5 ' . 22, the equation for output z1will be obtained. The circuit uses only NOR gates in its implementation.

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