By David Harris
As advances in expertise and circuit layout advance working frequencies of microprocessors, DSPs and different quickly chips, new layout demanding situations proceed to emerge. one of many significant functionality obstacles in latest chip designs is clock skew, the uncertainty in arrival instances among a couple of clocks. expanding clock frequencies are forcing many engineers to reconsider their timing budgets and to take advantage of skew-tolerant circuit thoughts for either domino and static circuits. whereas senior designers have lengthy constructed their very own options for lowering the sequencing overhead of domino circuits, this information has oftentimes been safe as exchange mystery and has hardly been shared. Skew-Tolerant Circuit layout offers a scientific manner of accomplishing an identical aim and places it within the fingers of all designers.This booklet basically offers skew-tolerant strategies and exhibits how they handle the demanding situations of clocking, latching, and clock skew. It offers the training circuit fashion designer with a essentially special instructional and an insightful precis of the newest literature on those serious clock skew matters. * Synthesizes the latest advances in skew-tolerant layout in a single cohesive educational* offers incisive guide and recommendation punctuated via funny illustrations* contains routines to check figuring out of key strategies and recommendations to chose workouts
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Extra info for Skew-Tolerant Circuit Design (The Morgan Kaufmann Series in Computer Architecture and Design)
Similarly, designers who believe latches are necessary to store state will be very confused by skew-tolerant domino circuits that eliminate the latches. On the other hand, it is easier to see that skew-tolerant domino circuits properly enforce sequencing and thus operate correctly. Finally, this view of sequencing dispels some myths about asynchronous systems. Some asynchronous proponents argue that asynchronous design is good because it eliminates clocking overhead by avoiding the distribution of high-speed clocks .
The clocks overlap enough that even under worst-case clock skews providing minimum overlap, the first gate B in the second phase has time to evaluate before the last gate A in the first phase begins precharge. As with static latches, the gates are guaranteed to be ready to operate when the data arrives even if skews cause modest variation in the arrival time of the clock. Therefore we do not need to budget clock skew in the cycle time. Another advantage of skew-tolerant domino circuits is that latches are not necessary within the domino pipeline.
The most effective would have been to use latches rather than flip-flops on the critical paths. This would have removed clock skew from the cycle time budget, relinquishing about 8 FO4 inverter delays for useful computation. Unfortunately, the ASIC house did not have experience with, or tools for, latchbased design, so this was not an option at the time. However, latch-based design has been practiced in the industry for decades and is supported by many CAD packages, so an investment in such capability would provide payoffs on many future high-speed designs.