Testing and Reliable Design of CMOS Circuits by Niraj K. Jha

By Niraj K. Jha

Within the previous few years CMOS know-how has develop into increas­ ingly dominant for knowing Very huge Scale built-in (VLSI) circuits. the recognition of this expertise is because of its excessive den­ sity and coffee strength requirement. the power to gain very com­ plex circuits on a unmarried chip has caused a revolution on this planet of electronics and pcs. besides the fact that, the swift develop­ ments during this zone pose many new difficulties within the zone of checking out. checking out has develop into a really time-consuming approach. with the intention to ease the load of trying out, many schemes for designing the circuit for superior testability were offered. those layout for testability options have started to be a focus for chip brands. the fad is in the direction of putting elevated emphasis on those ideas. one other byproduct of the rise within the complexity of chips is their larger susceptibility to faults. on the way to look after this challenge, we have to construct fault-tolerant platforms. the world of fault-tolerant computing has gradually received in significance. this day many universities provide classes within the parts of electronic method trying out and fault-tolerant computing. as a result of impor­ tance of CMOS know-how, a good portion of those classes will be dedicated to CMOS trying out. This e-book has been written as a reference textual content for such classes provided on the senior or graduate point. Familiarity with common sense layout and switching idea is believed. The e-book also needs to turn out to be necessary to execs operating within the semiconductor undefined.

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