By Daniel H. Sheingold
Классическая книга о том, как грамотно работать с различными датчиками. рассмотрены принципы действия различных активных и пассивных датчиков, приведено множество практических схем реализации аналогового интерфейса сопряжения датчиков в различных промышленных и измерительных системах. Подробно рассмотрены теоретические и практические аспекты подавления помех в аналоговых узлах. Анализированы источники систематических погрешностей и способы линеаризации нелинейных датчиков. Книга предназначена для разработчиков измерительных и промышленных систем.
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Extra resources for Transducer interfacing handbook: a guide to analog signal conditioning
In this thesis, the term ASIP exclusively refers to an instruction set oriented processor with application-speciﬁc optimizations including optional tightly-coupled hardware accelerators. 1 depicts typical classes of hardware implementation paradigms, which are bounded by pure ASICs on the left side and by general purpose processors on the right side. ASIPs can be viewed as a tradeoff between non-programmable application-speciﬁc integrated circuits (ASICs) and domain speciﬁc signal processors (DSSPs).
Moreover, parameters like area efﬁciency for low data-rate tasks and ﬂexibility requirements for errorprone and quickly changing control tasks have to be taken into account . It is possible for some algorithms to use adaptive implementations, where the number of operations that are needed for this task can be scaled to reduce energy. g. ). However, if the application permits a certain algorithmic degradation under some circumstances, it might be advantageous to detect this condition and scale the algorithm accordingly.
The total energy to perform a given computational task is unaffected by a reduction of f clk , if no additional changes are applied. A reduction of the effective switched capacitance Cdyn potentially results in a higher computational performance because of reduced interconnection and transition delays. Typically, this reduction has to be achieved using different hardware architectures or technologies. However, the minimization of Cdyn is limited by architectural bounds (due to the minimum required interconnection structure) and technological bounds (due to high interconnection capacitances and unavoidable short-circuit currents).