VLSI and computer architecture by Ravi Shankar; Eduardo B Fernandez

By Ravi Shankar; Eduardo B Fernandez

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This is a compact implementation with no static power dissipation. 9(e) [Mavo83] shows an alternative arrangement with enhancement mode transistors only. Here the control lines are formed in metal with short polysilicon stubs placed as needed to form transistors. This may be faster since the transistors are now connected in parallel and since the depletion mode transistors under certain conditions may approach cutoff. A natural extension is the programmable logic array (PLA) structure that will be discussed later under CMOS.

9(d) [Mavo83] shows the stick diagram representation for this example. (A stick diagram is a level of representation intermediate to the circuit and layout levels and abstracts the more important aspects of the layout for easy understanding of the underlying layout. In a stick diagram, a dashed line represents polysilicon layers, while diffusion and metal layers are represented by single and double solid lines, respectively. ) A series of polysilicon paths are placed orthogonal to diffusion paths and thus create enhancement mode transistors at each node.

2. Dynamic NMOS Logic Dynamic or clocked logic circuits have evolved from static logic circuits as a means of reducing power dissipation and silicon area while improving the speed. The basic characteristic of dynamic logic is that it employs charge storage on nodal capacitance to retain logic levels between clock 2. Silicon MOS Technology 30 r\vT (a) B > Out = G(A,B) ΐ < ΐ HE ΐ HE A > GO G1 G2 G3 (b) G(A,B) GO G1 G2 G3 (c) Fig. 9. (a) An «-type pass transistor, (b) A general logic functional block implemented with pass transistors alone, (c) Functional abstraction of Fig.

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