VLSI Chip Design with the Hardware Description Language by Ulrich Golze

By Ulrich Golze

This booklet introduces to trendy layout of enormous chips. a robust RISC processor within the diversity of a SPARC is apecified in a description language (HDL), it's constructed hierarchically and is eventually despatched as a gate version to the silicon seller LSI common sense for creation. The ensuing processor on a semi-custom gate-array chip with greater than 50.000 used gates and an potency of as much as forty MIPS is demonstrated on an automated try gear and a testboard. The ebook additionally introduces completely to the HDL VERILOG. The integrated disk includes greater than forty small and medium sized executable VERILOG examples, the big processor types and the VERILOG simulator VeriWell working on notebook or SPARC.

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Extra resources for VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design

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Requirements on the processor and its architecture are stated, and the methodology and project organization is fixed. The preliminary phase is included in Chapters 2 and 3. 3 The Design Phases <1>1 19 The Phase of External Specification and the Interpreter Model The processor behavior as visible for the outside user is specified. The behavior is mainly given by the instruction set. In addition to a verbal explanation of the instructions, an interpreter for executing arbitrary programs of these instructions is produced.

If we have a tester (ATE) as well, we may test the circuit again and intensively. This, however, will normally only be done for first prototypes and not in volume production. Such ATE tests are normally performed in slow motion, thus permitting only short test programs. Instead, we strive for a "real" test of the chip in a system or testboard similar to the later use in a real system. This is called a system environment. 8. The development of test patterns and testboards can be started in parallel to Phase «lIl, even though many details have to remain open.

Not only the bit pattern but also syntactical rules should be easily modifiable. 1 The RISe Processor at Work 49 processor is not a bottleneck and does not produce many costs. The reason lies in the simply structured RISC-typical instruction set. Therefore, encoding is not very critical and can be fixed at an early point in time. The assembler is supposed to generate the code for several target systems. In the early design phases, it supports various VERILOG models like the Interpreter Model or the Coarse Structure Model with a commented ASCII input file.

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