Wave Pipelining: Theory and CMOS Implementation by C. Thomas Gray

By C. Thomas Gray

The quest for greater functionality electronic platforms for purposes reminiscent of gen­ eral objective computing, signal/image processing, and telecommunications and an expanding expense recognition have resulted in an immense thrust for top velocity VLSI platforms carried out in low-cost and commonly to be had applied sciences similar to CMOS. This monograph, according to the 1st author's doctoral dissertation, con­ centrates at the means of wave pipelining as one approach towards reaching this target. the first concentration of this monograph is to supply a coherent pre­ sentation of the idea of wave pipelined operation of electronic circuits and to debate useful layout suggestions for the belief of wave pipelined circuits within the CMOS expertise. Wave pipelining should be utilized to numerous cir­ cuits for elevated functionality. for instance, many architectures that help systolic computation lend themselves to wave pipelined awareness. additionally, the wave pipeline layout technique emphasizes the function of managed clock skew in extracting better functionality from circuits that aren't deeply pipelined. Wave pipelining (also referred to as maximal cost pipelining) is a timing procedure­ ology utilized in electronic structures to extend the variety of powerful pipeline phases with no expanding the variety of actual registers within the pipeline. utilizing this system, new info is utilized to the inputs of a combinational good judgment block be­ fore the outputs as a result of past inputs can be found therefore successfully pipelining the combinational common sense and maximizing the usage of the logic.

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0 Therefore, it is obvious that the minimum clock period is achievable for any value of k since Tcile does not depend on k. Note that the clock skew (il) needed to achieve this minimum clock period does depend on k as shown in the following theorem. 3 The required intentional clock skew (il·) at the optimal clock period {T:,le} for the single stage system is (1-k )tmaz +ktmin +(1-k )t .. tup-kthold-kilt/+(1-k )ilt~+(1-k )iltr-kilt~+td for T:,le i- tinte"nalor the interval (tmaz -ktinte"nal+td+t ..

The combinational logic is described as a network of circuit elements. These circuit elements represent gates, collections of gates, or functional circuit blocks depending on the level of detail needed. 3 Single Stage Example Circuit Diagram through circuit elements. For notational convenience, a set g is defined representing the set of all nodes that are circuit element output nodes and a set o is defined representing the set of all nodes that are outputs of the combinational logic block (that is, feeding into the output register).

9. :\.. 16 Tel" Range VB. Ie (t ... ,=12, t",; .. 17 graphically depict the relationship between the and both ~ and k for fixed tmllz=12 and tmin=10. (26) Telk range Further differences in operation for different values of k will become more evident in Chapter 3 when multiple stage pipelines are investigated and in the discussion of the effect of variation on delay in Chapter 6. 39 Clock Period Constraints: Single Stage Systems 4~----~----~----~----~----~----~----~----. 5 :k=2 - , 'k=3 ••••.

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